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VIPROVE
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System status · as of 2026-07-30 Early Access

What runs. What is simulated.
What lies open.

Every claim on this site carries a chip: verified, simulated, PoC, open. This page is the balance sheet — with no upward rounding.

The chip system

Honesty as a design system.

The chips are not a disclaimer, they are the brand: the proof chip states what a claim carries — and what it does not (yet).

verified ✓ Measurement, recording or calculation with a source — reproducible on the page itself.
simulated Input from a recording or simulation, not measured live. Labeled instead of hidden.
PoC Works in the model, not yet on a real project. The gap is stated.
open The proof is still missing — and that is exactly what the page says, not the claim.
Standards landscape

Which edition applies — and where the check is missing.

ISO 13855:2024 Binding for DistanceCalc; the 2010 edition is superseded, changelog on the grammar page. ✓ binding
ISO 13855 · primary source Verify the S_M formula and Z values against the original standard text — the Pilz page was a secondary source. check open
ISO 13849 B1 + B3: safety zone and gap mapping; PLr assessment against real machine data pending. partial
ISO 26262 B2: ASIL-D architecture (CCU, 1oo2D, DC 99.8%) documented; live twin connection pending. architecture ✓
ASPICE B4: R1 coverage + R2 gating active; full rule pack in build. PoC
IEC 61496-3-3 ESPE type 3 referenced for 3D-ToF; 14 mm resolution in the video proof. referenced
Roadmap

What is built — and what comes next.

PHASE 2+3 Four proofs + home + grammar + integration, DE+EN, redirects live. ✓ done
PHASE 4 /stand (this page) · team + reality check rebuilt · legal pages. in build
PHASE 5 EN audit, performance budget, 301s from REDIRECTS.md to production. planned
Reality Check

The status on your data.

The reality check shows you the same status — only for your project: data-readiness, gaps, verdict. Two weeks, clearly scoped.