The Architecture Behind It
No data migration. No new silos. An intelligent graph layer over your existing toolchain.
Nine Adapters. One Graph. Zero Exports.
We don't move your data. We read it where it lives, normalize it into one graph model, and link it to the standards that govern your product. Your tools keep being the source of truth.
The only adapter that compiles.
Source-code adapters from other tools read diffs and file names. We parse the AST, derive the LLVM IR, and link every function to its requirement, ASIL class, and test case. The graph reaches the implementation — not just the documentation.
int safety_check(int x) { if (x > LIMIT) { return -1; } return 0; }
FunctionDecl ‘safety_check’ |-- ParmDecl ‘x’ : int L-- CompoundStmt |-- IfStmt | |-- BinaryOperator ‘>’ | L-- CompoundStmt | L-- ReturnStmt -1 L-- ReturnStmt 0
; linked to REQ-0427 — ASIL D define i32 @safety_check(i32 %x) { %cmp = icmp sgt i32 %x, 100 br i1 %cmp, label %then, label %end then: ret i32 -1 end: ret i32 0 }
From ALM chaos to an auditable graph in four stages.
A single pass through the engine ingests every adapter, normalizes the data into a uniform graph model, enriches it with the relevant clauses of your applicable norms, and produces gap reports an auditor can replay.
Pull, don't push
Adapters read items, revisions, and links from each source system via its native API. Nothing is written back. Nothing is mirrored.
One schema, eight dialects
Polarion items, Jira issues, EA elements, AST nodes, and IR functions all become nodes in the same graph model — typed, addressable, and version-stable.
Norm-aware linking
Clauses of your applicable norms (ISO 26262, ISO 21434, ASPICE, ISO 13849) are loaded as a second layer and linked to requirements via deterministic, auditable mappings.
Replayable gap analysis
Path walks, missing-edge detection, and coverage computation. Same input → same output, every time. Reports include the exact graph state they were generated from.
flowchart LR
subgraph SRC[" "]
direction TB
A1[Polarion]
A2[codeBeamer]
A3[Jira]
A4[Confluence]
A5[EA / MagicDraw / PlantUML]
A6[Source Code: libclang + LLVM IR]
A7[Git]
end
SRC --> B[Adapter Layer]
B --> C[Graph Model]
N[Norm Layer<br/>ISO 26262 — 21434<br/>21448 — ASPICE — 13849] --> C
C --> D[Analysis Engine]
D --> E[Gap Reports<br/>Traceability Matrix<br/>Coverage Heatmap]
classDef src fill:#f5f1e8,stroke:#e5dfd0,color:#3a4256
class A1,A2,A3,A4,A5,A6,A7 src
classDef core fill:#eef2ff,stroke:#c7d2fe,color:#1e3a8a
class B,C,D,E core
classDef norm fill:#fef3c7,stroke:#fcd34d,color:#b45309
class N norm
Property-Graph Model
Tool Integrations
- ALM: Polarion, Jama, Codebeamer
- Issue Tracking: Jira, Azure DevOps
- Version Control: GitLab, GitHub, Bitbucket
- CI/CD: Jenkins, GitLab CI
- Simulation: CARLA, MATLAB/Simulink
Deterministic Rule-Engine
Local LLMs (Privacy-First)
- Models: Llama 3, Mistral, customer fine-tunes
- Runtime: On-Premise or VPC
- Task: Topology → Narrative
Enterprise-Grade Security
- Encryption: AES-256 at rest, TLS 1.3 in transit
- Access Control: RBAC, SSO (SAML/OIDC)
- Audit Log: Every graph change is hashable and immutable
- Compliance: ISO 27001, GDPR, SOC2-ready
EA Model Generation — Architecture via API
Programmatic generation of SysML models from specifications. Schema-validated, MagicDraw-compatible.
Model Generator
Diagram Types
- SWE.5: Test Concept Diagrams
- Component: Architecture Overview
- Safety: Timing Extensions (QEA)
- SCT: Qualcomm ECU Allocation
Schema Layer
CI/CD Pipeline
- Trigger: Model-Change in MagicDraw
- Build: Auto-generate JSON + Diagrams
- Validate: Schema check + Safety rules
- Deploy: Graph-DB Update + Report